The present invention relates to a method for the programming an electrically programmable memory with a uniform field of data (e.g. all "1" values), and to memory architectures implementing such methods, especially to memories comprising a dynamic control interface, and most especially to flash EPROM type memories.
Memories with dynamic control interfaces have the necessary internal circuitry to carry out the internal sequencing of certain operations on the memory such as, for example, the programming operation. Flash EPROM memories typically include such circuitry.
It may be recalled that a flash EPROM memory is constituted by floating-gate memory cells having a gate oxide with a thickness that is small and uniform above the conduction channel. The cells are programmed by means of hot electrons. The total erasure of the memory is achieved by runnel effect.
These different operations use different voltage levels at the gates, sources and drains and particular periods of application of these levels. Each operation may be followed by a checking operation that consists of a reading of the programmed or erased cells, with reading voltage levels that are higher than in standard reading, to give the programming and erasing operations a high degree of reliability.
It is to simplify the use of memories such as these that an architecture with a control register has been proposed.
Flash EPROM type memories thus include a control register to receive instruction codes and circuitry to sequence the corresponding tasks. Generally, the external signals used are a write enable signal /WE, a signal to enable the output of the data elements in reading mode /OE, data signals such as for example D0-D7, address signals such as for example A0-A15, and connections for supply voltage VCC, high voltage VPP, and ground VSS. (By convention, the signals /OE and /WE are active in the low state.)
The first cycle awaited by the memory circuit is a cycle for the writing of an instruction code. This is done with the signal /OE in the inactive state (to inhibit the output of data elements on the signals D0-D7), while activating the write enable signal /WE and presenting, on the external data signals D0-D7, an instruction code that is memorized in the control register.
In the case of an instruction for the programming of a data element at a memory address, the next cycle awaited by the circuit is a cycle for writing the data element and the address. The programming is then triggered.
The memory circuit then awaits a new cycle for the writing of the instruction code for the verification of the programming. The effect of this writing operation is to stop the programming. The signal /OE is at the active level to enable the output, on the data signals D0-D7, of data that indicates whether or not the programming operation has been successful.
The duration of the programming is determined by the relative timing of the second cycle (for the writing of the data element to be programmed) which triggers the start of the programming operation, and the third cycle (for the writing of the verification instruction code) which triggers the stopping of the programming operation.
In the case of an erasure instruction, the control sequence is similar but simpler, because the erasure relates to the entire memory array (or to a sector when the array is segmented) and not to particular word addresses.
However, the erasure of the memory array requires all the memory array to be previously programmed so as to ensure a uniform and reliable erasure of the memory. If the erasure consists, by convention, in placing the memory cells in the logic state "1" and the programming, in placing the memory cells in the logic state "0", the entire memory has to be programmed in a uniform field of zero ("0") before the erasure is performed.
The total time of the programming control sequences for the entire memory array then becomes especially great since, as has been seen, it calls for three writing cycles for each memory address. For large-capacity memories, this time needed for the programming in a uniform field entails particularly heavy penalties for the user.
The manufacturer also suffers. Not only are the erasure test procedures slow, but also, more generally, testing and fault detection is made more difficult. The operations used for testing often include operations of programming a uniform field with complementary logic states for two adjacent cells in a word (known as the checkerboard test). (For example, such a test may require programming each memory byte with the data element 55.sub.H, i.e. binary 01010101.) Thus, the costs of the tests are very high.